In the past period of time, data center networks and servers were mainly accessed through 25G and 100G networks, and the most involved interfaces were SFP28 and QSFP28. The encoding used by both interfaces is 28 Gbps NRZ. With the rapid development of high-speed services such as big data, distributed storage, AI, and 5G, the scale of data center servers and networks has grown rapidly. The past 25G and 100G interface networks can no longer meet the current growth of big data services. TOR (Top of Rack) switches, the downlink rate has changed from 25G to 100G or even 200G. At the same time, major switch chip manufacturers have successively launched high-speed switching ASICs that support 56G-PAM4 since 2018. This further promotes the development of the data center switching rate and bandwidth to a higher 400G. The 100G QSFP28 interface cannot be directly matched with the switch chip supporting PAM4 due to the different speeds. In the process of upgrading TOR from NRZ to PAM4, there are two paths that can be taken. One is to upgrade from QSFP28 to QSFP56. The other is the commonly mentioned SFP-DD and DSFP, which are next-generation 100G interfaces. SFP-DD and DSFP are two different interface forms, and they are aimed at different users. The DSFP interface is used in the data centers of some Internet companies in China, but the application of DSFP is rarely introduced in various networks and journals. In view of this, based on the experience of actual project product design, the application of DSFP in data centers, especially TOR switches, is introduced. In the application, for communication and promotion.
As one of the next-generation 100G packaging forms, DSFP was launched and released its 1.0 specification by the Dual Small FormFactor Pluggable Multi-Source Agreement (DSFP MSA) in 2018. This specification defines DSFP’s I/O pins, electrical parameters and signals, power parameters, power levels, and the mechanical dimensions and specifications of SMT connectors and cages.
DSFP is launched by Amphenol, Finisar, Huawei, Molex, and other companies, aiming to provide 5G mobile with a higher-speed next-generation interface that is compatible with the current interface. Based on the currently widely used SFP+/SFP28 interface, DSFP can double the density of SFP+/SFP28 modules while occupying the same space, and realize high-density transmission on the basis of making full use of the existing size.
DSFP uses a 22-pin SMT connector with 0.8 mm pitch. It is different from the pin definition of SFP+/SFP28. Since DSFP adds two pairs of high-speed Serdes differential lines (a pair of TX and a pair of RX), DSFP is quite different from the definition of the previous SFP+ pins. The difference is as follows:
1) DSFP adds pin21 and pin22 to the SFP+20pin pin definition, where pin21 is next to pin11, and pin22 is next to pin1.
2) Canceled RS0, RS1, RXlos, TX_fault and TX_disable of SFP+.
3) pin6 is a Low Power Mode/Module Present (Mod_Abs) bidirectional multiplexing pin, and its Module Present is defined the same as Mod_Abs of SFP+/SFP28.
4) pin21 is the bidirectional multiplexing pin of Module Interrupt and Reset.
In general, DSFP sacrifices some low-speed signal pins for the increase of high-speed signals. The DSFP high-speed signal includes two receiving and two sending differential pairs. Physically, it can support two modes of single port and dual port. According to the specification, each lane of the DSFP module can support the rate of 9.95~53.1 Gbps, and the modulation mode is NRZ or PAM4.
The focus of the low-speed signal is two sets of bidirectional multiplexing pins LPWn/PRSn and INT/RSTn. Viewed from the direction of the DSFP optical module, LPWn and RSTn are input pins, and PRSn and INT are output pins.
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